Digital System Design 2025 — MAKAUT · EC-302 · Mid Sem PYQ with solutions

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Maulana Abul Kalam Azad University of Technology

Solutions

24 answers across 3 groups

Try each question first, then open it to check your answer.

Group AVery Short Answer Type Question · answer any 10 · 1 mark each

  1. I

    Which language can describe the hardware?

    Free sample

    Answer: Hardware Description Language (HDL)

    Explanation

    Languages such as VHDL and Verilog are used to describe and model digital hardware systems.

  2. II

    Write the Gray code of (1011)2(1011)_2.

  3. III

    What are the values of J and K of JK FF in the toggle state ?

  4. IV

    Which logic gate family needs least power consumption?

  5. V

    A D/AD/A converter has a ___ input and ___ output.

  6. VI

    2's complement of which 5-bit binary number is the same number?

  7. VII

    The S-R, J-K and D inputs are called ___ inputs.

  8. VIII

    S-R type flip-flop can be converted into D type flip-flop if S is connected to R through ___ gate.

  9. IX

    What do VHDL stand for?

  10. X

    1000 is a 2's complement number. Write the sign and magnitude of this number.

  11. XI

    Which gates having output logic '1'when all its inputs are at logic '0'?

  12. XII

    The resolution of 8 bit A/DA/D converter is ___ %.

Group BShort Answer Type Question · answer any 3 · 5 marks each

  1. 2

    Define the following terms:

    • i) Noise margin
    • ii) Fan-in
    • iii) Fan-out
    • iv) Power dissipation
    • v) Figure of Merit
    Show answer to question 2
  2. 3

    Compare VHDL and verilog.

  3. 4

    Design a combinational circuit using all discrete logic gates to convert BCD-to-excess-3 Code.

  4. 5

    Draw diagram and explain the working principle of 3 bit synchronous Up-Down counter.

  5. 6

    Minimize the following expression using K-map. Y(A,B,C,D)= m (1,2,5,6,9) + d(10,11,12,13,14,15)

Group CLong Answer Type Question · answer any 3 · 15 marks each

  1. 7(a)

    Briefly explain the operation of any one fast adder.

    5 marks
  2. 7(b)

    Design 4 bit composite adder in such a way that when external control signal =′1′=^{\prime}1^{\prime} it will behave as adder otherwise subtractor.

    6 marks
  3. 7(c)

    Implement a full adder using half adder and additional logic gates if required.

    4 marks
  4. 8(a)

    Draw the diagram for a MOD -10 Johnson counter using J-K flip-flops and determine its counting sequence. Draw the decoding circuit needed to decode each of the 10 states.

    10 marks
  5. 8(b)

    Draw and explain the operation of J-K Master Slave flip flop.

    5 marks
  6. 11(a)

    Design synchronous counter with a repeated sequence of states as follows: (ABC)-(000001011010111101 100-110-000 ........) Use D flip flop. Assume an input x, which control the forward and reverse transitions between the states.

    10 marks
  7. 11(b)

    Draw the circuit diagram for a MOD-64 parallel counter.

    5 marks

About this paper

The MAKAUT Digital System Design (EC-302) 2025 Mid Sem previous year question paper, set in semester 3. Download the verified PDF or read it online, then check your answers against the worked solutions above.

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Why solve Digital System Design PYQs?

Frequently asked questions

5 questions

What is the subject code for Digital System Design?

EC-302 is the MAKAUT subject code for Digital System Design.

Which exam is this Digital System Design question paper from?

The MAKAUT 2025 Mid Sem exam, semester 3. A student shared it, and it was checked before publishing.

Which branches is this Digital System Design paper for?

B.Tech Electronics and Communication Engineering.

Where can I find more EC-302 question papers?

On the Digital System Design subject page, which collects every year's papers along with notes and the syllabus.

Are there solutions for this paper?

Yes. Every question has a worked answer on this page, grouped like the paper. The first answer is free to read; sign in (it's free) to unlock the rest.

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